'Electronic 8-PIN SOIC thermal structural analysis' simulation project by bdelatti


#1

I created a new simulation project called 'Electronic 8-PIN SOIC thermal structural analysis':

This project shows the thermo-structural analysis of a 8 pin Small Outline Integrated Circuit (SOIC) chip with applied heat flux on the main chip core surfaces. It is a copy from another public project made by @ahmedhussain18 but this time the simulaiton ran using Code_Aster.


More of my public projects can be found here.


#2

Electronic chips are commonly used in a wide range of electronic circuits. Power loss normally occurs in these chips due to the rise in temperature which decreases their efficiency. This project shows the thermostructural analysis of a 8 pin Small Outline Integrated Circuit (SOIC) chip with applied heat flux on the main chip core surfaces. The geometry was provided by Shaun Houlihan and then imported to SimScale platform. The resulting geometry of a 8 pin Small Outline Integrated Circuit (SOIC) chip is shown in the figure below.

The geometry was meshed using tet-dominant with manual element sizing and custom mesh grading on SimScale platform. Thanks to the custom mesh grading, the curved surfaces such as fillets are captured properly with a good refinement level. The mesh is shown in the figure below.

For the analysis steady state thermostructural was selected since surface heat flux was considered to be static. Ceramic was selected as a material for the chip whereas copper was selected for its pins. A convective heat flux of 18 W/(m² K) was applied on all the outer faces of the chip. From bottom, pins were fixed in all directions and a volume heat flux of 6e7 W/m3 (300 mW (power dissipation)/5e-9 m3 (volume) was applied to the middle core. The figures below show the temperature and vonMises stress produced in the chip. It can be seen that the power loss of only 300 mW can lead to a temperature increase of around 505 K (~232 °C).